Whether stemming from malicious intent or natural occurrences, faults and errors can significantly undermine the reliability of lightweight architectures. In response to this challenge, fault detection plays a pivotal role in ensuring the secure deployment of cryptosystems. Even when a cryptosystem boasts mathematical security, its practical implementation may remain susceptible to exploitation through side-channel attacks. In this paper, we propose a lightweight fault detection architecture tailored for modular exponentiation, a building block of numerous cryptographic applications spanning from classical cryptography to post-quantum cryptography (PQC). Based on our simulations on ARM Cortex-A72 processor, our approach achieves an error detection ratio close to 100%, all while introducing a modest computational overhead of approximately 14%. Moreover, implementing our design on AMD/Xilinx Artix Ultrascale+ FPGA reported a minimal area and modest delay overhead compared to the unprotected design.