Scholarlink

This work presents a comparative evaluation of differential (8TD) and single-ended (8TS) 8T SRAM cell architectures designed using 32 nm CMOS technology, across a supply voltage range of 0.6 V to 1.2 V. At near-threshold operation ( \(V_{DD} = 0.6\,\text {V}\) ), the 8TD cell demonstrates a static noise margin (SNM) of 0.1932 V—representing a 26.7% improvement over the 8TS cell, which achieves 0.1525 V. Monte Carlo simulations with 2000 samples further confirm the 8TD cell’s robustness, exhibiting a standard deviation of only 5.6 mV in SNM, compared to 15.2 mV for the 8TS design—a reduction of over 60%. In terms of speed, the 8TD achieves a read delay of 340 ps versus 400 ps for the 8TS at 0.6 V, and maintains consistent write delays between 110–125 ps across voltage scaling. The 8TS cell, on the other hand, exhibits greater asymmetry and degradation in write performance at low voltages, particularly under write margin 0 conditions, where the access transistor connected to a low internal node must flip the cell. While the 8TD architecture involves additional control complexity and higher dynamic power due to differential sensing, it offers significantly better stability, variation tolerance, and access speed under low-voltage operation—making it a strong candidate for energy-efficient, variation-resilient memory systems.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design Trade-Offs in 8T SRAM Architectures: Differential and Single-Ended Approaches

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Ayush Dahiya,
  • Poornima Mittal,
  • Rajesh Rohilla

摘要

This work presents a comparative evaluation of differential (8TD) and single-ended (8TS) 8T SRAM cell architectures designed using 32 nm CMOS technology, across a supply voltage range of 0.6 V to 1.2 V. At near-threshold operation ( \(V_{DD} = 0.6\,\text {V}\) ), the 8TD cell demonstrates a static noise margin (SNM) of 0.1932 V—representing a 26.7% improvement over the 8TS cell, which achieves 0.1525 V. Monte Carlo simulations with 2000 samples further confirm the 8TD cell’s robustness, exhibiting a standard deviation of only 5.6 mV in SNM, compared to 15.2 mV for the 8TS design—a reduction of over 60%. In terms of speed, the 8TD achieves a read delay of 340 ps versus 400 ps for the 8TS at 0.6 V, and maintains consistent write delays between 110–125 ps across voltage scaling. The 8TS cell, on the other hand, exhibits greater asymmetry and degradation in write performance at low voltages, particularly under write margin 0 conditions, where the access transistor connected to a low internal node must flip the cell. While the 8TD architecture involves additional control complexity and higher dynamic power due to differential sensing, it offers significantly better stability, variation tolerance, and access speed under low-voltage operation—making it a strong candidate for energy-efficient, variation-resilient memory systems.