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Side-channel attacks remain a significant threat to cryptographic implementations on embedded systems, particularly those based on microcontrollers. Several protected implementations fail to provide sufficient robustness due to microarchitectural optimizations that often undermine their effectiveness. This work targets the ARM Cortex-M3, a widely deployed load-store architecture, and develops a cycle-accurate timing model for its Load (LDR) and Store (STR) instructions. We introduce \(\texttt {CycleSpy}\) , an open-source Python framework that automates the generation, execution, and timing analysis of assembly code on ARM Cortex-M3 microcontrollers without requiring expensive debugging tools. Through extensive experimentation, we characterize the timing behavior of memory instructions and identify the microarchitectural factors that influence their execution. Using these insights, we determine and validate an accurate predictive model that provides cycle-precise forecasts of Load and Store interactions with SRAM. The model is experimentally confirmed across four Cortex-M3 devices, and further applied to Cortex-M4 microcontrollers, where we identify important timing differences between the two architectures. Our findings deepen the understanding of instruction-level behavior in ARM microcontrollers and support the development of more secure cryptographic implementations.

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A Walk Down Memory Lane: Timing Analysis of Load and Store Instructions On ARM Cortex-M3 Devices

  • 会议论文

  • 发表日期：

    2026年

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  • Bas van der Zandt,
  • Senna van Hoek,
  • Durba Chatterjee,
  • Ileana Buhan

摘要

Side-channel attacks remain a significant threat to cryptographic implementations on embedded systems, particularly those based on microcontrollers. Several protected implementations fail to provide sufficient robustness due to microarchitectural optimizations that often undermine their effectiveness. This work targets the ARM Cortex-M3, a widely deployed load-store architecture, and develops a cycle-accurate timing model for its Load (LDR) and Store (STR) instructions. We introduce \(\texttt {CycleSpy}\) , an open-source Python framework that automates the generation, execution, and timing analysis of assembly code on ARM Cortex-M3 microcontrollers without requiring expensive debugging tools. Through extensive experimentation, we characterize the timing behavior of memory instructions and identify the microarchitectural factors that influence their execution. Using these insights, we determine and validate an accurate predictive model that provides cycle-precise forecasts of Load and Store interactions with SRAM. The model is experimentally confirmed across four Cortex-M3 devices, and further applied to Cortex-M4 microcontrollers, where we identify important timing differences between the two architectures. Our findings deepen the understanding of instruction-level behavior in ARM microcontrollers and support the development of more secure cryptographic implementations.