Cryptography currently plays a crucial role in ensuring secure communication and preventing unauthorized access to data. The strength of encryption systems heavily depends on various factors, with power consumption being a significant constraint. Consequently, numerous lightweight cryptography techniques have been developed and proposed to address this issue. In this paper, a modified version of the PRESENT cipher is implemented using a serial approach to replace the original PRESENT cipher. In comparison to the original PRESENT cipher, this version seeks to lower power usage. A minor element from TEA, another lightweight cipher, is also used into the suggested method. The modified PRESENT cipher has been developed using Xilinx’s Vivado 16.2 design suite at the Verilog level. Modified demonstrates significant advancement in power efficiency, consuming 78 mW, less complex and more efficient, compared to existing PRESENT’s 103 mW.

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Implementation of Modified Present Block Cipher Using Verilog

  • Anurag Verma,
  • Muzaffar Ali Khan,
  • Poonam Jindal

摘要

Cryptography currently plays a crucial role in ensuring secure communication and preventing unauthorized access to data. The strength of encryption systems heavily depends on various factors, with power consumption being a significant constraint. Consequently, numerous lightweight cryptography techniques have been developed and proposed to address this issue. In this paper, a modified version of the PRESENT cipher is implemented using a serial approach to replace the original PRESENT cipher. In comparison to the original PRESENT cipher, this version seeks to lower power usage. A minor element from TEA, another lightweight cipher, is also used into the suggested method. The modified PRESENT cipher has been developed using Xilinx’s Vivado 16.2 design suite at the Verilog level. Modified demonstrates significant advancement in power efficiency, consuming 78 mW, less complex and more efficient, compared to existing PRESENT’s 103 mW.