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The 65nm CMOS node is used for the development of DARE65T, an aerospace grade ASIC platform that can be used to design radiation-hardened-by-design ASICs with commercial foundry technology. The platform is composed of a range of IP libraries including standard cell, IO, SRAMs, as well as mixed signal IPs including PLL, current/voltage reference and ADC. All IPs are evaluated under irradiation by means of two different test vehicles, and a functional demonstrator ASIC is presented as a proof of platform readiness for flight model ASICs.

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Evaluation of the DARE65T Platform: Technology Study, IP Library Development and Demonstrator ASIC Design

  • 会议论文

  • 发表日期：

    2026年

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  • Marcel van de Burgwal,
  • Maxim Gorbunov,
  • Laurent Berti,
  • Lucas Tambara

摘要

The 65nm CMOS node is used for the development of DARE65T, an aerospace grade ASIC platform that can be used to design radiation-hardened-by-design ASICs with commercial foundry technology. The platform is composed of a range of IP libraries including standard cell, IO, SRAMs, as well as mixed signal IPs including PLL, current/voltage reference and ADC. All IPs are evaluated under irradiation by means of two different test vehicles, and a functional demonstrator ASIC is presented as a proof of platform readiness for flight model ASICs.