This study presents about the improving performance of Phase-Locked Loops using CNTFETs with circuit architecture along with its simulation results. There is no such work presented before which illustrate the complete PLL design using CNTFET. The schematic of simulation circuit is based on conventional design of Phase-Locked Loop. The model used is virtual source CNTFET model which describes enhancement mode, unipolar MOS transistors with semiconducting single walled CNT as channels. The model is based on a quasiballistic transport and embraces a precise explanation of the capacitor network in a CNTFET. All the circuit design and simulation performed in Cadence Virtuoso and general idea of layout taken from different references to get an approximate idea of area occupied by the PLL. As compared to PLL using MOSFET at 45 nm, 16 nm CNTFET based PLL gives approximately up to 33% more frequency signal at output, and consumes up to 90% less power and since there no design rule library for CNTFET it is rather derived from MOSIS rule (except transistor sizing) and found that area consumption of transistors also gets reduced by almost 45%. The dead zone is 1.5 ps which is approximately 46% less as compare to conventional PFD using CMOS at 16 nm technology node.