Fully integrated RC oscillators offer significant advantages in power consumption, integration level, and immunity against external clock tampering compared to oscillators that entail external references (e.g., crystal oscillators) [1]. Furthermore, for cost/area-constrained applications, on-chip RC oscillators with compensation can achieve satisfactory frequency stability, offering the possibility of replacing bulky crystal and MEMS oscillators [2–5]. In self-powered Internet-of-Things (IoT) applications, designing oscillators with a sub-0.5-V VDD can eliminate additional DC-DC converters to boost the VDD, thereby bolstering overall energy efficiency [6–8]. Frequency-locked loop (FLL) [8–10] featuring closed-loop operation exhibits enhanced resilience to VDD and temperature variations as the steady-state frequency is principally irrelevant to the delays of the comparator and digital logic, which are the major sources of frequency variations in open-loop relaxation oscillator [6, 7, 11, 12]. The work in [8] showcases a digital-intensive FLL capable of functioning at a sub-0.5-V VDD. Yet, due to the voltage headroom limitation imposed on the critical analog modules, the line sensitivity (11%/V) and long-term stability (400 ppm) of the FLL are compromised.