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Efficient finite field multiplication over GF( \(2^m\) ) is essential for high-performance elliptic curve cryptography (ECC) on resource-constrained hardware. This paper presents a recursive modular Karatsuba multiplier for GF( \(2^{m}\) ) that integrates modular reduction within a 5-stage stagewise recursive pipeline, achieving one result per clock cycle. The proposed architecture reduces logic depth, balances pipeline stages, and minimizes resource usage (875 LUTs and 1,371 registers on a Xilinx Artix-7 FPGA), while maintaining a low critical path delay (4.2 ns). Experimental results demonstrate significant improvements in area–delay product (ADP) compared to state-of-the-art multipliers. The design is scalable to larger NIST binary fields (e.g., B-233, B-283, B-409, B-571) and supports energy-efficient operation, making it suitable for high-speed, low-power ECC accelerators in embedded and IoT systems.

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High-Performance FPGA Implementation of a Recursive Modular Karatsuba Multiplier over  \(GF(2^m)\)

  • 会议论文

  • 发表日期：

    2026年

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  • Ruby Kumari,
  • Sumeet Saurav,
  • Abhijit Karmakar

摘要

Efficient finite field multiplication over GF( \(2^m\) ) is essential for high-performance elliptic curve cryptography (ECC) on resource-constrained hardware. This paper presents a recursive modular Karatsuba multiplier for GF( \(2^{m}\) ) that integrates modular reduction within a 5-stage stagewise recursive pipeline, achieving one result per clock cycle. The proposed architecture reduces logic depth, balances pipeline stages, and minimizes resource usage (875 LUTs and 1,371 registers on a Xilinx Artix-7 FPGA), while maintaining a low critical path delay (4.2 ns). Experimental results demonstrate significant improvements in area–delay product (ADP) compared to state-of-the-art multipliers. The design is scalable to larger NIST binary fields (e.g., B-233, B-283, B-409, B-571) and supports energy-efficient operation, making it suitable for high-speed, low-power ECC accelerators in embedded and IoT systems.