Nowadays, energy or power dissipation has become a major concern in digital integrated circuit design. This high-density design of the chip increases power dissipation. One of the primary causes of energy dissipation is irreversible computation, necessitating improved power optimisation techniques. Consequently, the reversible logic methodology provides an efficient means to minimise energy dissipation in the circuit. Addition is a fundamental arithmetic operation that underpins other regularly utilised operations, including multiplication, division, and subtraction. In computing systems, adders, which are digital circuits that add numbers, are a fundamental component. With the continuous development of technology, the need for efficient and high-performance processing units has become inevitable, and these must be made from reversible logic elements. The Carry Skip Adder (CSA) is among the most efficient adders utilised in numerous data processing units to do swift arithmetic operations. This study introduces a design that is effective of a CSA utilising reversible logic gates and evaluates its performance. The proposed design achieves notable improvements over existing works by reducing garbage outputs, optimizing constant inputs, minimizing delay, enhancing quantum cost efficiency, and decreasing the overall gate count. Additionally, the performance of the suggested adder surpasses that of others in terms of transistor count and power dissipation.