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The modern Internet of Things applications require low power implementation. The static random access memory (SRAM) being the most power consuming component of silicon on chip. This work compares the loop-cutting 10T SRAM cell parameters for 45 nm and 90 nm technology nodes. Further, the parameters of loop-cutting 10T SRAM are compared with industrial 6T (6T) SRAM bit-cell and Asymmetric 8T (ASY8T) SRAM bit-cell. The leakage power dissipation of loop-cutting 10T SRAM is reduced by 1.06 \(\times \) /1.23 \(\times \) compared to 6T/ASY8T respectively. The read and write power dissipation of loop-cutting 10T SRAM is reduced by 1.70 \(\times \) /0.90 \(\times \) and 1.70 \(\times \) /0.86 \(\times \) compared to 6T/ ASY8T, respectively. The read and write delay of loop-cutting 10T SRAM is reduced by 1.30 \(\times \) /0.78 \(\times \) and 1.30 \(\times \) /1.24 \(\times \) compared to 6T/ASY8T, respectively. The comparison has been at 0.7 V supply voltage using cadence virtuoso simulator at 45nm technology node.

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Performance Assessment of Loop-Cutting 10T Static Random Access Memory Cell For High Performance Computation

  • 会议论文

  • 发表日期：

    2026年

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  • Priyanka Bansal,
  • Anish Paul,
  • Shaminder Kaur,
  • Ashish Sachdeva

摘要

The modern Internet of Things applications require low power implementation. The static random access memory (SRAM) being the most power consuming component of silicon on chip. This work compares the loop-cutting 10T SRAM cell parameters for 45 nm and 90 nm technology nodes. Further, the parameters of loop-cutting 10T SRAM are compared with industrial 6T (6T) SRAM bit-cell and Asymmetric 8T (ASY8T) SRAM bit-cell. The leakage power dissipation of loop-cutting 10T SRAM is reduced by 1.06 \(\times \) /1.23 \(\times \) compared to 6T/ASY8T respectively. The read and write power dissipation of loop-cutting 10T SRAM is reduced by 1.70 \(\times \) /0.90 \(\times \) and 1.70 \(\times \) /0.86 \(\times \) compared to 6T/ ASY8T, respectively. The read and write delay of loop-cutting 10T SRAM is reduced by 1.30 \(\times \) /0.78 \(\times \) and 1.30 \(\times \) /1.24 \(\times \) compared to 6T/ASY8T, respectively. The comparison has been at 0.7 V supply voltage using cadence virtuoso simulator at 45nm technology node.