The continued scaling of CMOS technology presents increasing challenges in the design of energy-efficient and high-performance static random-access memory (SRAM), primarily due to heightened concerns around power dissipation and leakage currents. This paper examines three configurations of the conventional 6T SRAM cell—standard, sleep, and dual-threshold—tailored for low-power operation. In the sleep configuration, an additional PMOS transistor is introduced to minimize leakage during idle periods, while the dual-threshold configuration replaces standard PMOS transistors with high-threshold variants to further reduce leakage. Using GPDK 45 nm technology and a supply voltage range from 0.5 V to 1 V, the performance of each configuration is assessed with respect to power consumption, access time, and leakage power. The findings indicate that both the sleep and dual-threshold designs significantly lower write power dissipation and leakage compared to the standard configuration, though with a slight trade-off in write access time. These results underscore the potential of these configurations for achieving power-efficient SRAM cells in future ultra-low-power applications.