Field-Programmable Gate Arrays (FPGAs) are widely utilized in educational and research contexts to teach digital logic design, system-level design, and hardware-software integration. Despite their pedagogical and practical significance, FPGA learning environments often present challenges due to steep learning curves, a lack of collaborative design platforms, scattered open-source toolchains, vendor-specific development environments, and limited real-time support. Recent advancements in Large Language Models (LLMs) offer promising opportunities to address these issues through intelligent support systems. This study proposes a new architecture to integrate an LLM-aided chatbot into FPGA learning platforms, which feature a Code Module and a Mentor Module, to enhance both FPGA education and research. The Code Module is designed to assist with hardware description language (HDL) code generation, verification, correction, and conversion between high- and low-level code. The Mentor Module addresses conceptual queries, recommends appropriate IP cores from the IP library, and generates basic quiz questions from lecture slides to support learner self-assessment. The proposed platform architecture is theoretically evaluated based on interdisciplinary state-of-the-art literature in FPGA learning platforms, intelligent tutoring systems, and the application of LLMs in educational platforms. Additionally, a qualitative evaluation of the prototype of the proposed platform architecture has been conducted to investigate its effectiveness, demonstrating high levels of user satisfaction. However, the outcome of this study is a well-grounded framework for incorporating LLM-based chatbots into FPGA learning platforms, enhancing learner autonomy, alleviating instructional bottlenecks, and promoting more accessible FPGA education and research.