This paper presents a scalable software-hardware co-design platform to demonstrate floating point (FP) operations in scientific computing. The system-on-chip (SoC) architecture is built on the AMD-Xilinx Python Productivity for Zynq (PYNQ) framework, integrating an ARM Cortex-A9 MPCore with the AMD/Xilinx Zynq-based PYNQ field-programmable gate array (FPGA). As a case study, the platform presents the implementation of a trigonometric function, one of the FP operations from the OpenFPU design library—executed on the FPGA and controlled by software through Jupyter Notebooks. The framework is designed to be scalable and extensible, supporting a wide range of FP operations and hardware accelerators, including FP adders and multipliers, Fourier transforms, matrix processing, and linear algebra computations. The evaluation results show a significant acceleration to the FP operations over the specialized hardware design on the FPGA.