Multiplication is a fundamental operation in digital systems, multiplication is frequently utilized in high-performance computing, embedded systems, and DSP. High latency and power consumption are problems with conventional multipliers that call for optimized architectures. This work introduces a 32-bit pipelined Wallace Tree multiplier that uses a pipelined architecture to increase throughput and decrease partial product accumulation delay, hence improving performance and efficiency. Verilog is used to implement the design, Xilinx Vivado is used to synthesize it, and timing and power performance are examined. With a positive timing slack of 3.262 ns and a power con sumption of just 0.189 W, the proposed multiplier outperforms non-pipelined solutions in terms of performance and power consumption. The results validate the suitability of this design for low-power, high-speed VLSI applications. Optimized maths can be explored in future improvements.