Security has become a paramount concern across various domains, with advancements in Human–Computer Interaction (HCI) significantly enhancing security measures through machine learning technologies. Recent developments in machine learning have revolutionized face recognition systems, improving accuracy and efficiency. However, achieving optimal performance in face recognition tasks often requires addressing challenges related to speed and computational complexity. This study explores the role of Field-Programmable Gate Arrays (FPGAs) for face recognition systems, addressing these challenges through parallel processing, reconfigurability and hardware-based optimization. The key findings of this survey highlight the latest FPGA-based designs, optimization techniques and algorithms aimed at achieving targeted performance metrics. Also, the paper provides an in-depth examination of different approaches and methodologies used in FPGA implementations, showcasing the evolution of systems in addressing the growing demands for efficiency and accuracy in face recognition tasks. Additionally, this study identifies critical challenges, such as efficient weight storage and computation balancing, which require a redesign using Vedic Mathematics. The need for a plug-and-play modularity approach to manage trade-offs between accuracy and complexity is also emphasized. The contributions of this survey include comprehensive analysis of recent FPGA-based face recognition implementations, an examination of fundamental concepts and principles underlying the reviewed works, and an identification of future research directions. Notably, the study concludes that the limited availability of general-purpose FPGA-based deep learning libraries and toolchains remains a key area for exploration. By presenting these insights, the paper provides valuable guidance to researchers and practitioners, who seek to leverage FPGA technologies for enhanced face recognition applications.