Accurate wirelength estimation at the placement stage is critical for guiding physical design decisions in digital integrated circuits, as wirelength strongly influences timing, power consumption, and overall placement quality. However, true wirelength values are only available after detailed routing, a process that is computationally intensive and time-consuming—especially for large-scale designs implemented in advanced technology nodes. Early-stage prediction of wirelength enables more accurate timing delays prediction, power consumption, improving the assessment of placement quality before routing begins. This work proposes five machine learning models to wirelength prediction based solely on placement-level information: a fully connected neural network, XGBoost, and three graph neural networks incorporating GCN, GAT, and GraphSAGE layers. The models are trained on a dataset of 32 blocks designed in a 28 nm technology node, with logical and layout features extracted from graph-based netlist representations. Experimental results show that the GraphSAGE-based network demonstrates the best performance, achieving a mean absolute error (MAE) of \(2.8\,\mu \textrm{m}\) and a mean absolute percentage error (MAPE) of 16%, significantly outperforming the HPWL baseline (MAE = \(5.2\,\mu \textrm{m}\) , MAPE = 72%).