Significant challenges in further increasing processors performance are caused by physical and technological limitations at the current level of hardware development. In this context, software-hardware co-design technologies gain particular importance. These technologies represent one of the promising research and development directions for the coming decades. This paper explores the prospects of implementing a new cross-product instruction in processors based on the free and open RISC-V architecture, as well as possible performance gains when solving computational tasks. We demonstrate the complete flow of performed actions, starting from the idea of implementing a new command, its prototyping, evaluating performance using the Gem5 simulator, and culminating with embedding the instruction into the GCC compiler and providing a specific usage example.