The AHB to APB Bridge is crucial component in System-on-Chip (SoC) designs, Achieving efficient communication between the pipelined AHB bus and the non-pipelined APB bus. In the proposed work a AHB to APB bridge is built using a bridge architecture which enables to translate pipelined, burst-oriented, high speed AHB transactions into sequential, low-power APB transactions by maintaining synchronization and data integrity. It was developed with a FSM to manage transactions and pipelining to maintain efficiency. Verification was performed using a Universal Verification Methodology testbench environment through direct and random testcases of burst, single, sequential, non-sequential transactions. 80 testcases were tested to obtain a functional coverage of 88%.