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In this paper, it is explore the decoder design by comparing conventional logic gates and advanced transistor techniques. The first segment of this proposal revolves around the design of a 2-to-4 decoder with 4T and 3T logic (state-of-the-art) and its assessment on performance parameters. The second segment deals with the design of a 3-to-8 decoder employing either 6T NAND & 5T NAND gates, while paying close attention to the power, delay and performance for comparison. In case of 2-to-4 decoder the average power consumption, delay and power delay product are reduced by19.32%, 57.02% and 65.21%. Similarly, in 3-to-8 decoder the average power consumption, delay and power delay product are reduced by 21.11%, 40% and 5.33%. We hope that it would help in investigating the benefits and limitations of the various methods and to look at the trade-offs in performance choices for different digital applications. This will inspire by comparing these two architectures.

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Design of Decoders Circuits Using Advanced 3T Transistor Techniques

  • 会议论文

  • 发表日期：

    2025年

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  • R. Hanuma Naik,
  • P. V. Gopi Krishna Rao,
  • M. Eswar,
  • B. Ankitha,
  • B. Nagaraju,
  • C. Dhananjayudu

摘要

In this paper, it is explore the decoder design by comparing conventional logic gates and advanced transistor techniques. The first segment of this proposal revolves around the design of a 2-to-4 decoder with 4T and 3T logic (state-of-the-art) and its assessment on performance parameters. The second segment deals with the design of a 3-to-8 decoder employing either 6T NAND & 5T NAND gates, while paying close attention to the power, delay and performance for comparison. In case of 2-to-4 decoder the average power consumption, delay and power delay product are reduced by19.32%, 57.02% and 65.21%. Similarly, in 3-to-8 decoder the average power consumption, delay and power delay product are reduced by 21.11%, 40% and 5.33%. We hope that it would help in investigating the benefits and limitations of the various methods and to look at the trade-offs in performance choices for different digital applications. This will inspire by comparing these two architectures.