Implementation of Memristor Based 8T SRAM Cells for Optimizing Noise Voltage Reliability
摘要
Today, the latest impressive evolution and adaptation has been achieved by VLSI technology and advancement is also going on this field. To reach these platforms, this credit goes to scaling down the aspect ratio. The measurements of the MOSFETs have not been reduced, but also the rebellion is moving all circuits from MOSFET to one new emerging device. Memristor is a modern category of device that can be used to construct memristive structure, systems and memories that the mathematical models can prove and the models can be reliable in terms of physical system behavior. Static Random Access Memory (SRAM) is a memory device that connects directly to the CPU. By incorporating a memristor into the SRAM design, the non-volatile behavior of the cell can be achieved while retaining the operational flexibility of traditional volatile SRAM cells. Memristor based SRAM is an innovative new technology with specific low-power, high-density, low noise-voltage (NV) and good scalability properties. This paper highlights the analysis of the new issue of reliability, i.e. NV which affecting the SRAM cell retention voltage. For comparison with the effect of aspect ratio using Cadence Virtuoso tool, simulation results are taken on the Memristor based 8T SRAM cell and the conventional 8T SRAM cell with 45 nm technology.