Minimizing power consumption is a critical challenge in digital circuit design, particularly in Arithmetic Logic Units (ALUs), which significantly impact processor performance. Full adders, as fundamental components of ALUs, play a crucial role in executing arithmetic operations. Optimizing their design leads to substantial improvements in computational efficiency. This paper presents a power-efficient full adder circuit using XOR-XNOR logic, aimed at reducing energy consumption. To further enhance performance, Complementary Metal Oxide Semiconductor (CMOS) and transmission gate logic are integrated, leveraging their advantages in power efficiency and switching characteristics. Additionally, hybrid logic techniques are employed to optimize key parameters, such as power consumption and transistor count, ensuring a balance between efficiency and resource utilization. The proposed design improves overall circuit performance while minimizing power dissipation, making it a viable solution for low-power applications using Generic Process Design Kit (GPDK) 90nm technology node.