The growing demand for energy-efficient and thermally reliable integrated circuits highlights the necessity of optimizing CMOS inverter design, with particular attention to transistor sizing and temperature resilience. This study systematically investigates the influence of transistor width variations and thermal conditions on CMOS inverter power consumption using the Cadence Virtuoso simulation platform. Four distinct scenarios are examined: varying PMOS width while keeping NMOS width constant, varying NMOS width with fixed PMOS width, and analyzing temperature-dependent power behavior for both narrow (120 nm) and wide (520 nm) transistor configurations. The simulation outcomes reveal a consistent trend where increasing the width of either transistor results in elevated dynamic and static power dissipation. This increase is primarily attributed to enhanced gate capacitance and leakage currents. Across all conditions, NMOS transistors exhibit higher power consumption compared to PMOS transistors. Furthermore, elevated operating temperatures contribute to a noticeable rise in power consumption for both device types, emphasizing the need for thermal-aware design strategies. Quantitative analysis shows that expanding PMOS width from 120 to 520 nm, with NMOS width held constant, leads to a 13.86% increase in total power consumption. In contrast, varying NMOS width under constant PMOS width results in a 15.84% rise. Additionally, power consumption increases by 2.49% when both transistor widths are 120 nm, and by 1.618% when both are 520 nm, over a specified temperature range. These findings underscore the importance of meticulous transistor sizing and thermal management in the design of low-power CMOS circuits, particularly for compact, high-performance applications such as Internet of Things (IoT) and wearable devices.