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The paper discusses the hardware implementation of a high-speed Lorenz chaotic system is proposed, leveraging an approximate-multiplier based computation. The system is implemented using the Fourth-Order Runge Kutta (RK4) method, structured as a Finite State Machine to ensure precise iterative updates. The design is tested and validated through simulation in Xilinx Vivado using Verilog and the hardware implementation is performed on FPGA board Spartan7 (xc7s100fgga676-2).

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Delay-Optimized Approximate Realization Technique for Chaotic Systems (DART)

  • 会议论文

  • 发表日期：

    2026年

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  • Apoorva Banerjee,
  • Saurabh Chauhan,
  • Vansh Singh,
  • Kriti Suneja

摘要

The paper discusses the hardware implementation of a high-speed Lorenz chaotic system is proposed, leveraging an approximate-multiplier based computation. The system is implemented using the Fourth-Order Runge Kutta (RK4) method, structured as a Finite State Machine to ensure precise iterative updates. The design is tested and validated through simulation in Xilinx Vivado using Verilog and the hardware implementation is performed on FPGA board Spartan7 (xc7s100fgga676-2).