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Deploying deep neural networks in ultra-low-power tiny embedded devices has inspired research on compression techniques such as pruning, mixed-precision quantization, and approximation-aware training methods to reduce memory requirements and computational complexity during inference. However, most tiny processors or microcontrollers currently employed for the inference task do not include support for vector or sub-byte integer arithmetic operations, such as those utilized in quantized convolutional neural network (CNN) models. Hence, they need to run programs with additional instructions for packing and unpacking coefficients. Focusing on the multiply-accumulate operations that dominate CNN runtime, we present a SIMD (single instruction, multiple data) accelerator tightly coupled into a RISC-V processor pipeline. This accelerator is capable of receiving packed coefficients in 8-bit and 4-bit formats and outputting their dot product. Moreover, to reduce hardware costs and lower the latency of the SIMD unit, we propose an approximate multiplier structure which considers shared resources for 8 \(\times \) 8-bit and 4 \(\times \) 4-bit multiplications. Additionally, the level of approximation can be configured at synthesis time to trade hardware resources off with accuracy. The SIMD accelerator has been implemented as a custom function unit within a VexRiscv core synthesized for an FPGA and evaluated by running CNN ResNet models for image classification using the CIFAR-10 dataset.

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A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices

  • 会议论文

  • 发表日期：

    2026年

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  • José Juan Hernández Morales,
  • Frank Hannig,
  • Jürgen Teich

摘要

Deploying deep neural networks in ultra-low-power tiny embedded devices has inspired research on compression techniques such as pruning, mixed-precision quantization, and approximation-aware training methods to reduce memory requirements and computational complexity during inference. However, most tiny processors or microcontrollers currently employed for the inference task do not include support for vector or sub-byte integer arithmetic operations, such as those utilized in quantized convolutional neural network (CNN) models. Hence, they need to run programs with additional instructions for packing and unpacking coefficients. Focusing on the multiply-accumulate operations that dominate CNN runtime, we present a SIMD (single instruction, multiple data) accelerator tightly coupled into a RISC-V processor pipeline. This accelerator is capable of receiving packed coefficients in 8-bit and 4-bit formats and outputting their dot product. Moreover, to reduce hardware costs and lower the latency of the SIMD unit, we propose an approximate multiplier structure which considers shared resources for 8 \(\times \) 8-bit and 4 \(\times \) 4-bit multiplications. Additionally, the level of approximation can be configured at synthesis time to trade hardware resources off with accuracy. The SIMD accelerator has been implemented as a custom function unit within a VexRiscv core synthesized for an FPGA and evaluated by running CNN ResNet models for image classification using the CIFAR-10 dataset.