The implementations of deep learning algorithms on embedded and edge devices often face challenges such as energy efficiency, scalability, throughput, and the need for real-time processing in resource-constrained environments. To tackle the challenges in this domain, we have developed STANN, an open-source hardware-software co-design workflow for both training and inference of deep learning algorithms on Field-Programmable Gate Arrays (FPGAs). In this paper, we show the implementation of one-dimensional layers, including convolutional layers, more data type options, an automatic code generator based on a high-level Python description, and a complete end-to-end FPGA workflow. Based on the SECOM dataset targeting the detection of failures in semiconductor manufacturing, we implemented hardware accelerators with convolutional layers on an Xilinx Ultra96-V2 board using STANN for classification. With an accuracy of 97.45 %, the one-dimensional convolution algorithm shows advantages for time-series data over other algorithms like random forest. Using the lightweight embedded FPGA platform, an execution time of 131 µs can be achieved, nearly three times faster than the baseline using a desktop CPU.