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Approximate computation plays an important role in the VLSI implementation of arithmetic architectures for multimedia and image processing applications. These error-tolerant arithmetic circuits reduce the complexity of the architecture in terms of area, delay, and power with acceptable accuracy. In this paper, an imprecise multiplier is proposed using area and power-efficient 4:2 compressors for the Two Dimensional Finite Impulse Response Filter Architectures (2DFIRA). In the multiplier, at the partial products reduction stage, a few bits are truncated to zero to reduce the hardware blocks and MSB bits are summated by an exact 4:2 compressor. The remaining product terms are summed up by proposed approximate compressors. The hardware blocks of the proposed multiplier are implemented by mixed logic design rather than static CMOS design. The approximated multiplier and approximate compressor architectures with fewer transistors improve the VLSI design metrics than exact multiplier architectures. The proposed multiplier and 2DFIRA is implemented in Full Custom Virtuso tools from Cadence in 45nm CMOS technology.

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VLSI Implementation of a Low Power-Area-Delay Efficient Approximate Multiplier for 2D FIR Filter Architectures

  • 会议论文

  • 发表日期：

    2026年

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  • Venkata Krishna Odugu,
  • Harish Babu Gade,
  • C. Venkata Narasimhulu,
  • E. Bharat Babu

摘要

Approximate computation plays an important role in the VLSI implementation of arithmetic architectures for multimedia and image processing applications. These error-tolerant arithmetic circuits reduce the complexity of the architecture in terms of area, delay, and power with acceptable accuracy. In this paper, an imprecise multiplier is proposed using area and power-efficient 4:2 compressors for the Two Dimensional Finite Impulse Response Filter Architectures (2DFIRA). In the multiplier, at the partial products reduction stage, a few bits are truncated to zero to reduce the hardware blocks and MSB bits are summated by an exact 4:2 compressor. The remaining product terms are summed up by proposed approximate compressors. The hardware blocks of the proposed multiplier are implemented by mixed logic design rather than static CMOS design. The approximated multiplier and approximate compressor architectures with fewer transistors improve the VLSI design metrics than exact multiplier architectures. The proposed multiplier and 2DFIRA is implemented in Full Custom Virtuso tools from Cadence in 45nm CMOS technology.