In industrial applications, it is important to transmit critical data in a timely and reliable manner to ensure safe and efficient operation. Time Sensitive Networking (TSN) provides mechanisms to support this, including time synchronization, traffic shaping and scheduling. Traffic shaping is particularly important as it helps to regulate the flow of network traffic and prevent congestion. The proposed work deals with the FPGA design and implementation of an effective Traffic Shaper architecture for TSN applications. The hybrid Traffic Shaper architecture is mapped to an FPGA-based design using the Xilinx Vivado Tool. The results show that the proposed architecture provides a better throughput and latency performance compared to other Traffic Shaper architectures. The proposed design methodology provides an efficient and cost-effective solution for TSN Traffic Shaper architectures in FPGA-based designs.