The raising need for artificial intelligence applications poses new demands on computer hardware and algorithm development. Both faster processing and lower power consumption are needed. Dataflow hardware proves to be more energy-efficient due to lower frequencies and more dense computing compared to control-flow programming. However, the utilization of dataflow chip die surface is not uniform. The diversity is the result of dataflow hardware implementation of algorithms and diversity in algorithm execution. If an algorithm is presented as a dataflow graph, certain paths might be utilized more than others. However, each path requires a certain amount of FPGA resources comparable to the length of the path. This work aims to present a new model for controlling frequencies of dataflow kernels adjusted to the expected amount of processing of available kernels. Results indicate that trading between frequencies of certain kernels can improve the execution speed of the dataflow hardware, without jeopardizing the durability of the chip die due to the overall heating.