In the era of edge computing, where IoT devices are increasingly connected to the Internet, data security and privacy have become critical concerns. Steganography, a technique for embedding hidden information within digital media, offers a lightweight security measure that complements traditional cryptographic methods. However, implementing steganographic techniques efficiently in edge devices poses challenges related to computational overhead, power consumption, and real-time performance. This paper introduces a lightweight FPGA-based steganography accelerator core designed for edge computing platforms. Our design optimizes resource efficiency, low latency, and adaptability while ensuring robust data hiding and retrieval capabilities. The proposed system is evaluated with respect to hardware utilization, power efficiency, and embedding performance. We evaluated our system on the Xilinx Kria KV260 edge computing platform, analyzing hardware utilization, execution time, power consumption, and throughput across different image sizes. Experimental results demonstrate that our FPGA-based accelerator outperforms a traditional ARM processor-based software implementation, achieving up to 2.42 \(\times \) speed-up with dual-core configurations. Furthermore, power efficiency analysis shows that the system effectively minimizes energy consumption, making it suitable for power-sensitive edge applications. The proposed solution is highly adaptable and can be integrated with other hardware accelerators, such as video encoding or network security modules, to enhance processing capabilities in IoT environments.