Analog-to-digital converters (ADCs) such as successive approximation register (SAR) rely on accurate reference voltage circuits (RVCs) to ensure precise signal conversion. This work examines how charge-redistribution (CR) and charge-sharing (CS) SAR-ADCs impact the design of the buffer, considering different RVC scheme and digital-to-analog converters architectures (DAC). CR-based SAR-ADCs require high-speed buffers due to continuous bit-dependent connections, leading to demanding power and bandwidth requirements. In contrast, CS-based SAR-ADCs, which operate passively during conversion, allow for relaxed buffer design with lower dominant pole frequency and improved power efficiency. Analytical expressions for the reference buffer behavior, including voltage accuracy and settling time, are derived for binary-weighted and C-2C CR- and CS-based SAR ADCs.