This work introduces a Multi-Factor Scaling (MFS) framework to utilize Spin-Orbit-Torque Magnetic RAM (SOT-MRAM) as a substitute for traditional SRAM caches, which face scalability and efficiency issues with CMOS technology down-scaling. With distinct read/write paths and superior endurance, SOT-MRAM is evaluated for artificial intelligence (AI), natural language processing (NLP), and general-purpose applications. The MFS framework assesses the impact of SOT-MRAM on-chip cache design through Design Space Exploration (DSE) and density replacement studies, comparing it against SRAM configurations. The research proposes and explores a Physically Split Cache (PSC) design with Virtual Reordering (VRO) to manage Write Variation (WVAR) dynamically, aiming to prolong cache lifetime and reliability. Furthermore, the potential of SOT-MRAM to replace DRAM in main memory is investigated despite the challenge of limited parameter availability with reliable simulations.