In modern times, engineers have searched for ways to bridge the many gaps between software and hardware, taking advantage of various techniques, methods, and algorithms. A well-known example of this phenomenon is the introduction of Deep Learning Super Sampling (DLSS - NVIDIA Article ) as a method of offloading part of the rendering burden onto Artificial Intelligence (AI) models. Meanwhile, in the realm of compiler development, similar tendencies have emerged, with the primary goal of assuaging classical compiler optimization challenges by improving loop unrolling and instruction scheduling to reduce latency and upward code size trends. This paper aims to analyse the feasibility of contemporary autotuning methods [3, 15] as part of the compilation process in CPU applications, mainly focusing on tile size optimization. This study aims to highlight the potential performance improvements assessed in cache misses per program, with our experiments showing that, generally, optimizing tile sizes for cache efficiency alone can yield up to a \(\approx 98.1\%\) improvement in reducing atom-level cache misses in single-threaded scenarios. With modern software’s growing complexity and hardware advancements’ slowdown, traditional heuristics and compiler optimizations are steadily becoming insufficient. These findings suggest that compiler autotuning could become the next important step in compiler optimization.