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This chapter presents a radiation-tolerant 13-bit ADC that was realized in 65 nm CMOS technology and whose development took into account the compromises and considerations from the radiation-tolerant ADC design trade-offs. A Semi-time-interleaved pipelined-SAR structure is used, which provides both power efficiency and SEE tolerance. Each sub-block of the proposed ADC is made radiation tolerant for TID and SEE at both architectural and circuit levels. Through electronic measurements, the prototype ADC achieves 70.79 dB SNDR and 80.26 dB SFDR at the Nyquist input frequency and a sampling rate of 80 MS/s. In addition, TID irradiation tests confirm that the ADC remains unaffected up to 500 krad(Si) and has a robust withstand capability. The ADC has a limited SEE-sensitive range and also recovers quickly from SEE events.

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13-Bit High-Performance Radiation-Tolerant ADC

  • 章节

  • 发表日期：

    2026年

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  • Zheyi Li,
  • Laurent Berti,
  • Paul Leroux

摘要

This chapter presents a radiation-tolerant 13-bit ADC that was realized in 65 nm CMOS technology and whose development took into account the compromises and considerations from the radiation-tolerant ADC design trade-offs. A Semi-time-interleaved pipelined-SAR structure is used, which provides both power efficiency and SEE tolerance. Each sub-block of the proposed ADC is made radiation tolerant for TID and SEE at both architectural and circuit levels. Through electronic measurements, the prototype ADC achieves 70.79 dB SNDR and 80.26 dB SFDR at the Nyquist input frequency and a sampling rate of 80 MS/s. In addition, TID irradiation tests confirm that the ADC remains unaffected up to 500 krad(Si) and has a robust withstand capability. The ADC has a limited SEE-sensitive range and also recovers quickly from SEE events.