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In this chapter, we present the process of performance evaluation of CMOS technology against radiation effects, which serves as a fundamental cornerstone for the subsequent radiation-tolerant design. We then present a comprehensive radiation-tolerant ASIC/IC design flow that builds on the conventional ASIC/IC design process and includes additional steps to account for radiation effects. All tests and steps ensure both electrical performance and radiation tolerance.

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Radiation Hardened IC Design and Evaluation Flow

  • 章节

  • 发表日期：

    2026年

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  • Zheyi Li,
  • Laurent Berti,
  • Paul Leroux

摘要

In this chapter, we present the process of performance evaluation of CMOS technology against radiation effects, which serves as a fundamental cornerstone for the subsequent radiation-tolerant design. We then present a comprehensive radiation-tolerant ASIC/IC design flow that builds on the conventional ASIC/IC design process and includes additional steps to account for radiation effects. All tests and steps ensure both electrical performance and radiation tolerance.