I am fascinated with ring oscillators. They are simple, elegant oscillating circuits; they do not need a frequency-determining network in their simplest form. In Fig. 5.1a, I show a ring oscillator made of three inverters. The last inverter’s output is connected to the first inverter’s input. \(C_{1}\) , \(C_{2}\) , and \(C_{3}\) are parasitic capacitors that exist between the gate, drain, source, and channel, as well as the capacitance between the metal interconnects and the bulk silicon. These parasitic capacitances make the ring oscillator oscillate because it takes time to charge and discharge a capacitor, and the signal propagation through the inverter is delayed. We call these delays propagation delays in technical jargon, one going high to low and the other going low to high. You see the input and output of the first inverter in Fig. 5.1b. The rising edge of a pulse at the input arrives at the output after a delay \(t_{PHL}\) . Likewise, the falling edge at the input takes \(t_{PLH}\) time to arrive at the output. The delay times are measured between the 50% points of the signal swing. The average of the two delays is denoted by \(t_{P}\) : \(\displaystyle t_{P}=\frac {t_{PHL}+t_{PLH}}{2}. \)