This paper proposes a shift register design using latch based technique. Shift registers are the most repetitively used block in a circuit, which reduces the overall power consumption and area of the circuit. They play a vital role in signal processing, image processing, and digital signal modulation and demodulation. The primary objective of this paper is to develop a shift register architecture that reduces both power and area utilization without compromising functionality. The prominent approaches include reducing the transistor count, which is strategically reducing both the power consumption and area of the chip. Firstly, latch-based storage components are used in the shift register rather than flip-flops because latches generally require less power and space than flip-flops. By carefully designing and optimizing the latch circuits, power consumption and area are reduced while maintaining reliable data storage and propagation. Performance comparisons were made between flip-flop-based shift register and latch-based shift register designs in 45 nm and 90 nm CMOS technologies.