Due to CMOS technology’s higher power consumption and lower device density, it faces serious challenges in digital logic design. Overcoming the restrictions of conventional CMOS technology, Quantum-dot Cellular Automata (QCA) presents a viable way to construct ultra-small circuits. The fundamental building block for building QCA logic circuits is the QCA cell, which is made up of four two-electron quantum dots. The majority gate and inverters are the essential parts of QCA. In order to ensure correct synchronization and information transmission inside a circuit, clocking serves a key part. Regular clocking also encourages scalability and tackles manufacturing issues in the nanoscale area. This article aims to realize the Full Subtractor circuit using various regular clocking schemes. This work also provides a detailed comparison-based analysis between the clocking-based circuits with respect to the basic parameters in QCA. According to this study, the circuits’ performance is remarkable when realized with modified 1-D clocking.