This study delves into the pivotal domain of quantum circuits for arithmetic operations, essential for the peripherals of quantum computing. Leveraging the advantages of reversible gates, such as reduced power consumption and lower latency, this research underscores the efficient deployment of quantum circuits, with special focus on the judicious use of Clifford +T gates due to their elevated implementation costs. The design introduces an optimized quantum full adder (QFA) circuit, aiming for T-count minimization through the exclusive use of a single CCNOT (Toffoli) gate, thereby enhancing efficiency and resource utilization. Furthermore, the study presents a quantum integer multiplication circuit employing the proposed QFA, achieving greater T-count savings compared to current alternatives. The proposed quantum multiplier reduces the Tcount to 220 while generating only 17 Ancilla and Garbage Outputs. Employing Verilog HDL for practical implementation, synthesis, and physical design in Cadence-Genus and Innovus at the 90 nm technology node, within an ASIC design flow, results in an average power dissipation of 2.736 nW and a latency of 4.01 ns. This multiplier also contributes to the development of a third-order IIR filter, with an average power dissipation of 29.28 nW.