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This chapter focuses on designing macro-cells and RAM-cells using OpenLane. It explains the process of hardening designs as macros and integrating them into a chip-level design, using an Arithmetic Logic Unit (ALU) as an example. The chapter also covers the design of SRAM cells, including their architecture and integration into digital systems. Practical examples and configuration files are provided to guide users through the process of creating and integrating macros and RAM-cells in OpenLane.

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Macro-Cells and RAM-Cells with OpenLane

  • 章节

  • 发表日期：

    2025年

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  • Susana Ortega Cisneros,
  • Emilio Isaac Baungarten Leon,
  • Pedro Mejia Alvarez

摘要

This chapter focuses on designing macro-cells and RAM-cells using OpenLane. It explains the process of hardening designs as macros and integrating them into a chip-level design, using an Arithmetic Logic Unit (ALU) as an example. The chapter also covers the design of SRAM cells, including their architecture and integration into digital systems. Practical examples and configuration files are provided to guide users through the process of creating and integrating macros and RAM-cells in OpenLane.