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This paper presents a preliminary study that evaluates the initial development board supporting the stable RISC-V Vector-1.0 ISA, with a specific focus on the integration of RISC-V and SYCL technologies. This research utilizes the SYCL-Bench benchmark suite to assess a SYCL implementation based on both clang and gcc compilers. Meanwhile gcc lacks autovectorization support for RISC-V, clang exhibits poor speedups. Significantly, a code refactors in a contemporary SYCL-style led to improved performance, achieving nearly 77% of the peak speedup compared to the auto-vectorized counterparts.

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Exploring Performance in RISC-V Vector Architecture: A Preliminary Study Integrating RISC-V and SYCL

  • 会议论文

  • 发表日期：

    2025年

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  • Enrique de la Calle Montilla,
  • Francisco Igual,
  • Carlos García Sánchez

摘要

This paper presents a preliminary study that evaluates the initial development board supporting the stable RISC-V Vector-1.0 ISA, with a specific focus on the integration of RISC-V and SYCL technologies. This research utilizes the SYCL-Bench benchmark suite to assess a SYCL implementation based on both clang and gcc compilers. Meanwhile gcc lacks autovectorization support for RISC-V, clang exhibits poor speedups. Significantly, a code refactors in a contemporary SYCL-style led to improved performance, achieving nearly 77% of the peak speedup compared to the auto-vectorized counterparts.