Quantum computing emerges as a pivotal solution to classical computing limitations in the post-Moore era, offering superior capabilities through qubits’ unique properties of superposition, entanglement and interference. Actually, we are in the Noisy Intermediate-Scale Quantum where quantum devices present challenges in circuit design. This work proposes optimized implementations of Binary Coded Decimal adders using Clifford+T gates. With a focus on mitigating the computational costs associated with T-gates and the error rates of CNOT gates, two distinct designs are presented. The first design prioritizes minimizing T-gate usage, leading to significant reductions in T-count and T-depth, while slightly decreasing the number of CNOT gates. The second design targets minimizing CNOT gate usage, resulting in a 15% reduction in CNOT gates, alongside notable reductions in T-count and T-depth. Leveraging the capabilities of the Clifford+T gate set, both designs showcase a balance between efficiency and error mitigation.