Coarse-Grained Reconfigurable Arrays (CGRAs) are a programmable architectural solution that efficiently supports the execution of computation-intensive application functions (kernels). Compilers for CGRAs typically focus on optimizing the mapping of single loops, whose body can be expressed in a basic block produced by a compiler front-end. This approach, while effective in leveraging spatial parallelism within data flows, restricts the scope of deployment and neglects opportunities stemming from control flow analysis. To enhance the code coverage of CGRA compilers, the end-to-end compilation framework presented in this paper operates at the kernel level, considering both Data Flow Graph (DFG)-based and Control Flow Graph (CFG)-based optimizations. Its implementation, based on the MLIR infrastructure, includes a front-end for Intermediate Representation (IR) abstraction, an optional middle-end reshaping the IR to facilitate modulo scheduling, a kernel mapper for operation allocation that supports both DFG and CFG mapping optimizations, and a back-end that performs register allocation and generates assembly with the mapped solution. The entire framework pipeline is fully automated and is released as open-source software (Code available at https://github.com/esl-epfl/Compigra.git ).