This paper presents a novel circuit architecture for counting frequently occurring items (aka Heavy Items) in filtered data streams. The circuit is designed as a kernel in a multi-kernel system that can be synthesized with High-Level Synthesis (HLS) tools for Field Programmable Gate Arrays (FPGAs). The proposed kernel serves as an interface between a frequency estimation sketch configured as a data stream filter and a host processor that monitors the items in the filtered data stream. While recent work has focused on demonstrating high-throughput implementations of generic standalone frequency estimation sketches using FPGAs, the proposed work addresses the need for efficient interfacing between these sketches and a host processor. In particular, this paper demonstrates how the frequency of thousands of heavy items can be monitored entirely on-chip using an FPGA optimized key-value store circuit architecture. Implementing this architecture using the FPGA Support Package for the Intel OneAPI compiler showed good scalability and high throughput that easily matches or surpasses the throughputs of existing state-of-the-art FPGA implementations of frequency estimation sketches.