Design and Performance Evaluation of an Energy-Efficient 16x16 SRAM Memory Array for Low Power Applications
摘要
Memory plays a vital role in any semiconductor device. There are two types of memory: SRAM (static random access memory) and DRAM (dynamic random access memory). Major design limitations include small functional space, power consumption, and latency to design any electronic component. Power consumption is one such factor which needs optimization in Memory. This article is related to designing of 16X16 memory array using 6T SRAM. The optimization was done in the sense amplifier in the memory architecture where the power consumption of the circuit is optimized from 447 micro watts to 350 micro watts. The delay of the circuit is also optimized from 225 ns to 133 ns. The design is implemented in cadence virtuoso tool.