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In this chapter, the characteristics of the Si depletion mode MOSFET (DMM) devices are analyzed from the point of view of its use as the non-linear resistance for the BaSIC topology. Based on the analysis, the parameters of the internal device structure are varied to improve the trade-off between reducing the saturation current of the device and its on-resistance. In particular, reducing the gate oxide thickness is shown to significantly improve this trade-off curve. In addition, the UMOSFET structure is shown to be much superior to the DMOSFET structure. Significantly lower on-resistances are predicted for an optimized Si DMM device with the saturation current level needed to extend the short-circuit withstand time beyond 10 μs for commercially available 1.2 kV SiC power MOSFETs.

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Optimization of Si DMM

  • 章节

  • 发表日期：

    2025年

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  • B. Jayant Baliga,
  • Ajit Kanale

摘要

In this chapter, the characteristics of the Si depletion mode MOSFET (DMM) devices are analyzed from the point of view of its use as the non-linear resistance for the BaSIC topology. Based on the analysis, the parameters of the internal device structure are varied to improve the trade-off between reducing the saturation current of the device and its on-resistance. In particular, reducing the gate oxide thickness is shown to significantly improve this trade-off curve. In addition, the UMOSFET structure is shown to be much superior to the DMOSFET structure. Significantly lower on-resistances are predicted for an optimized Si DMM device with the saturation current level needed to extend the short-circuit withstand time beyond 10 μs for commercially available 1.2 kV SiC power MOSFETs.