The BaSIC topology with a gate source shorted silicon depletion mode MOSFET (DMM) in series with the source electrode was shown to be effective for improving the short-circuit withstand time of a SiC power MOSFET in Chap. 5 . These results were gathered by using a single SiC power MOSFET with current rating of 6 A. Many applications require greater levels of current. This is commonly achieved by either paralleling of discrete devices or by the fabrication of multi-chip modules. The excellent paralleling of the BaSIC topology for increasing the current handling capability of SiC power MOSFETs is described in this chapter.