The BaSIC topology with a gate source shorted silicon depletion mode MOSFET (DMM) in series with the source electrode was shown to be effective for improving the short-circuit withstand time of a SiC power MOSFET in Chap. 5 . The power semiconductor industry manufactures a large variety of Si enhancement mode MOSFETs (EMMs) with low on-state resistances due to their widespread applications. It is therefore advantageous to utilize one of these EMM devices for the BaSIC topology applied to the SiC power MOSFET. The DC gate bias applied to the Si EMM device can be programmed by the power electronics engineer based on the short-circuit withstand time required for a particular application. This provides a unique flexibility for the power electronics engineer while using a single commercially available SiC power MOSFET. Trade-off curves between the short-circuit withstand time and the increase in on-resistance and switching energy loss achieved with the BaSIC(EMM) topology are contrasted with these alternate approaches.