A self-timed data-driven processor (DDP) is one of the promising embedded processor architectures realizing high-performance and low-power operations. The DDP is implemented by a self-timed pipeline (STP) circuit, i.e., asynchronous circuits. In order to realize a practical embedded system employing the DDP, the DDP could play a powerful accelerator with a commodity application processor. In such a case, an I/F circuit with buffers is required to synchronize operation timing, convert data transfer control protocols, and perform data input/output according to the DDP’s pipeline processing capability. This paper proposes a reliable I/F circuit using asynchronous FIFOs that guarantee a required MTBF with minimized synchronization circuits. The prototype circuit operating at 50 MHz clock frequency is implemented and evaluated on an FPGA chip. Results demonstrate that it achieves over 3.8 times higher input/output throughput while maintaining comparable reliability to a synchronous FIFO-based I/F circuit. Furthermore, it has been shown that the proposed I/F circuit outperforms the synchronous FIFO-based I/F circuit in terms of throughput per resource.