This work presents new hardware architectures for the Galois Counter Mode of operation used for authenticated encryption/decryption. In common Galois Counter Mode implementations, Advance Encryption Standard in counter mode is used for encryption and decryption. Authentication tag is computed by repeated multiplication and addition of encrypted message in the field \(\mathbb {F}_{2^{128}}\) . Sub-quadratic Toeplitz matrix vector product based binary multiplier architectures are used for the implementation of binary field \(\mathbb {F}_{2^{128}}\) . For optimal implementation, encryption/decryption function and the multiplication in \(\mathbb {F}_{2^{128}}\) should be balanced in time, i.e., take approximately the same number of clock cycles to perform a single operation on one block. The architectures proposed in this paper are designed to offer low to medium throughputs with logic requirements that reflect the performance level. We report and compare implementation results of three different architectures using application specific integrated circuits.