Multi-bit Digital-to-Analog Converters (DACs) are essential components, converting a digital input stream into an analog output waveform. However, one of the key challenges in their design and implementation is managing it’s inherent nonlinearity characteristic. Due to manufacturing tolerances, the DAC weights suffer from slight variations in the actual values of these components. Even small mismatches lead to significant nonlinearity, especially in high-resolution DACs. This chapter demonstrates how the current sources of a current-steering DAC are tuned by means of the transistor back-gate with 2 nA precision. The requirements for back-gate tuning are theoretically derived and translated into calibration requirements for the DAC at the circuit level. To correct the DAC errors, they must first be estimated using a suitable algorithm, which is described in detail in this work. The proposed concept is then implemented in a continuous-time (CT) Sigma Delta modulator with a bandwidth of 30 MHz and an internal quantization resolution of 5 bits. The approach to DAC linearization and the underlying theory are thoroughly validated through measurements of a prototype fabricated in 22 nm FDSOI CMOS technology. The comparison with other state-of-the-art modulators with similar bandwidth reveals an outstanding figure of merit, which is attributed to the high energy efficiency of the introduced linearization technique.